1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to a transaction request servicing mechanism for communication buses.
2. Description of the Prior Art
Efficient data communication between master devices and slave devices in data processing systems is a key factor in enhancing system performance. Data communication is typically mediated by communication buses and associated bus protocols. Examples of bus protocols are the Advanced Microprocessor Bus Architecture (AMBA™) family of protocols, which are suitable for system-on-chip bussing requirements, and was developed by ARM Limited of Cambridge, England.
It is known to send transaction requests, such as read requests and write requests, from a master device to a slave device via a bus with master identification (ID) information that identifies the source of the data. Known bus protocols provide that slave devices obey certain ordering constraints for the order of servicing of transaction requests from master devices. Such ordering constraints ensure that processing tasks are efficiently carried out without corrupting stored data or other problems which can arise with out of order servicing. Typically, some transaction requests will be more critical to system performance than others, for example an instruction fetch in the presence of an interrupt is a high priority transaction. Accordingly, in addition to master ID information and ordering constraints it is desirable to send transaction priority information along the bus. However, backwards compatibility of bus protocols is an important consideration in bus protocol development and so the addition of extra side-band signals to known bus protocols to accommodate priority information is problematic.